1. Field of the Invention
The present invention relates to a method of forming wiring structure and a semiconductor device, and in particular to a technique preferably applicable to so-called dual damascene process in which a connection hole and a wiring groove are separately formed in an insulating film on a semiconductor substrate, and a Cu wiring is formed using Cu (alloy) as a conductive material.
2. Description of the Related Art
There are accelerated trends in micronization and introduction of multi-layered wiring structure as semiconductor devices are becoming more highly integrated and chip size is shrunk. In logic device having such multi-layered wiring structure, wiring delay is becoming a dominant factor of device signal delay. The device signal delay is in proportion to a product of wiring resistance and wiring capacitance, so that reduction in the wiring resistance and wiring capacitance is important in order to improve the wiring delay.
One known investigation for reducing the wiring resistance is made on use of Cu, which is a low-resistance metal, as a material forming the wiring. It is, however, extremely difficult to pattern Cu to form the wiring, so that there is proposed a method, so-called dual damascene process, in which a connection hole (via-hole) and a wiring groove are formed in an insulating film, which are later filled with Cu to form the wiring.
The damascene process is roughly classified into single damascene process in which the via-hole and wiring groove are separately formed, and dual damascene process in which the via-hole and wiring groove are formed at the same time. The dual damascene process may be supposed to enjoy more opportunities of use in consideration of an advantage of reducing the number of process steps, but a disadvantage thereof resides in its narrow process margin because the via-hole and wiring groove must be processed at the same time. In particular in recent advancement in micronization of the wiring, a margin allowable for the pattern processing is becoming narrower, and this raises public attention to the single damascene process which can ensure a wider process margin than in the dual damascene process.
[Patent Document 1] Japanese Patent Application No. 2002-318674